PXR40RM Datasheet, PDF (1069/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
NOTE
The trigger overrun flag will not set for CFIFOs configured for software
trigger mode.
27.7.4.7.5 Command Sequence Non-Coherency Detection
The EQADC provides a mechanism to indicate if a command sequence has been completely executed
without interruptions. A command sequence is defined as a group of consecutive commands bound for the
same CBuffer and it is expected to be executed without interruptions. A command sequence is coherent if
its commands are executed in order without interruptions. Since commands are stored in the CBuffers
before being executed in the EQADC, a command sequence is coherent if, while it is transferring
commands to a CBuffer, the buffer is only fed with commands from that sequence without ever becoming
empty.
A command sequence starts when:
• a CFIFO in TRIGGERED state transfers its first command to CBuffer.
• the CFIFO is constantly transferring commands and the previous command sequence ended.
• the CFIFO resumes command transfers after being interrupted.
And a command sequence ends when:
• an asserted EOQ bit is detected on the last transferred command.
• CFIFO is in edge-trigger mode and asserted PAUSE bit is detected on the last transferred
command.
• the CBuffer to which the next command is bound is different from the one to which the last
command was transferred.
Figure 27-57 shows examples of how the EQADC would detect command sequences when transferring
commands from a CFIFO to a CBuffer. The smallest possible command sequence can have a single
command as shown in example 3 of Figure 27-57.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-87