PXR40RM Datasheet, PDF (896/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
entry. In Slave mode the DSPI only responds to transfers initiated by a bus master external to the DSPI
and the SPI command field of the TX FIFO entry is ignored.
25.4.3.1 Master Mode
In SPI Master Mode the DSPI initiates the serial transfers by controlling the Serial Communications Clock
(SCK) and the Peripheral Chip Select (PCS) signals. The SPI command field in the executing TX FIFO
entry determines which CTAR registers will be used to set the transfer attributes and which PCS signal to
assert. The command field also contains various bits that help with queue management and transfer
protocol. See Section 25.3.2.6, DSPI PUSH TX FIFO Register (DSPI_PUSHR), for details on the SPI
command fields. The data field in the executing TX FIFO entry is loaded into the shift register and shifted
out on the Serial Out (SOUT) pin. In SPI Master Mode, each SPI frame to be transmitted has a command
associated with it allowing for transfer attribute control on a frame by frame basis.
25.4.3.2 Slave Mode
In SPI Slave Mode the DSPI responds to transfers initiated by a SPI bus master. The DSPI does not initiate
transfers. Certain transfer attributes such as clock polarity, clock phase and frame size must be set for
successful communication with a SPI master. The SPI Slave Mode transfer attributes are set in the
DSPI_CTAR0.
25.4.3.3 FIFO Disable Operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The DSPI
operates as a double-buffered simplified SPI when the FIFOs are disabled. The TX and RX FIFOs are
disabled separately. The TX FIFO is disabled by writing a ‘1’ to the DIS_TXF bit in the DSPI_MCR. The
RX FIFO is disabled by writing a ‘1’ to the DIS_RXF bit in the DSPI_MCR.
The FIFO Disable mechanisms are transparent to the user and to host software; Transmit data and
commands are written to the DSPI_PUSHR and received data is read from the DSPI_POPR.When the TX
FIFO is disabled the TFFF, TFUF and TXCTR fields in DSPI_SR behave as if there is a one-entry FIFO
but the contents of the DSPI_TXFR registers and TXNXTPTR are undefined. When the RX FIFO is
disabled the RFDF, RFOF and RXCTR fields in the DSPI_SR behave as if there is a one-entry FIFO but
the contents of the DSPI_RXFR registers and POPNXTPTR are undefined.
25.4.3.4 Transmit First In First Out (TX FIFO) Buffering Mechanism
The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds
four words, each consisting of a command field and a data field. SPI commands and data are added to the
TX FIFO by writing to the DSPI PUSH TX FIFO Register (DSPI_PUSHR). TX FIFO entries can only be
removed from the TX FIFO by being shifted out or by flushing the TX FIFO.
The TX FIFO Counter field (TXCTR) in the DSPI Status Register (DSPI_SR) indicates the number of
valid entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data
is transferred into the shift register from the TX FIFO.
The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during the next transfer. The
TXNXTPTR contains the positive offset from DSPI_TXFR0 in number of 32-bit registers. For example,
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor