PXR40RM Datasheet, PDF (1372/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
NOTE
The OVC bits within the DC1 register can be set to delay the CPU to
alleviate (but not eliminate) potential overrun situations.
Error information is messaged out in the following format (see Table 31-19):
3
2
1
ECODE (00110 / 01000)
SRC
TCODE (001000)
msb
5 bits
4 bits
6 bits
lsb
Fixed length = 15 bits
Figure 31-38. Error Message Format
31.14.7.4 Watchpoint Timing Diagram (Two MDO and One MSEO Configuration)
MCKO
Watchpoint
Error
MSEO
MDO[1:0]
11 11 00 00 10 00 00 00 10 00 00 10 01 00
WPM:
TCODE = 15
Source Processor = 0b00
Watchpoint Number = 2
Error:
TCODE = 8
Source Processor = 0b00
Error Code = 6 (Queue Overrun – WPM Only)
Figure 31-39. Watchpoint Message and Watchpoint Error Message
31.14.8 NZ7C3 Read/Write Access to Memory-Mapped Resources
The read/write access feature allows access to memory-mapped resources via the JTAG/OnCE port. The
read/write mechanism supports single as well as block reads and writes to e200z7 system bus resources.
The NZ7C3 module is capable of accessing resources on the e200z7 system bus, with multiple
configurable priority levels. Memory-mapped registers and other non-cached memory can be accessed via
the standard memory map settings.
All accesses are setup and initiated by the read/write access control/status register (RWCS), as well as the
read/write access address (RWA) and read/write access data registers (RWD).
Using the read/write access registers (RWCS/RWA/RWD), memory-mapped e200z7 system bus resources
can be accessed through NZ7C3. The following subsections describe the steps which are required to access
memory-mapped resources.
NOTE
Read/write access can only access memory mapped resources when system
reset is de-asserted.
Misaligned accesses are NOT supported in the e200z7 Nexus3 module.
31-56
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor