PXR40RM Datasheet, PDF (857/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexCAN Module
Registers. The bit is set when the corresponding buffer completes a successful transmission/reception and
is cleared when the CPU writes it to ‘1’ (unless another interrupt is generated at the same time).
NOTE
It must be guaranteed that the CPU only clears the bit causing the current
interrupt. For this reason, bit manipulation instructions (BSET) must not be
used to clear interrupt flags. These instructions may cause accidental
clearing of interrupt flags which are set after entering the current interrupt
service routine.
If the Rx FIFO is enabled (bit FEN on FLEXCAN_x_MCR set), the interrupts corresponding to MBs 0 to
7 have a different behavior. Bit 7 of the FLEXCAN_x_IFLAG1 becomes the “FIFO Overflow” flag; bit 6
becomes the FIFO Warning flag, bit 5 becomes the “Frames Available in FIFO flag” and bits 4-0 are
unused. See Section 24.3.4.12, Interrupt Flags 1 Register (FLEXCAN_x_IFLAG1), for more information.
A combined interrupt for all MBs is also generated by an Or of all the interrupt sources from MBs. This
interrupt gets generated when any of the MBs generates an interrupt. In this case the CPU must read the
IFLAG Registers to determine which MB caused the interrupt.
The other 4 interrupt sources (Bus Off, Error, Tx Warning, and Rx Warning) generate interrupts like the
MB ones, and can be read from the Error and Status Register. The Bus Off, Error, Tx Warning and Rx
Warning interrupt mask bits are located in the Control Register.
24.4.11 Bus Interface
The CPU access to FlexCAN registers are subject to the following rules:
• Read and write access to supervisor registers in User Mode results in access error.
• Read and write access to unimplemented or reserved address space also results in access error. Any
access to unimplemented MB or Rx Individual Mask Register locations results in access error. Any
access to the Rx Individual Mask Register space when the MBFEN bit in FLEXCAN_x_MCR is
negated results in access error.
• If MAXMB is programmed with a value smaller than the available number of MBs, then the
unused memory space can be used as general purpose RAM space. Note that the Rx Individual
Mask Registers can only be accessed in Freeze Mode, and this is still true for unused space within
this memory. Note also that reserved words within RAM cannot be used. As an example, suppose
FlexCAN is configured with 64 MBs and MAXMB is programmed with zero. The maximum
number of MBs in this case becomes one. The MB memory starts at 0x0060, but the space from
0x0060 to 0x007F is reserved (for SMB usage), and the space from 0x0080 to 0x008F is used by
the one MB. This leaves us with the available space from 0x0090 to 0x047F. The available memory
in the Mask Registers space would be from 0x0884 to 0x097F.
NOTE
Unused MB space must not be used as general purpose RAM while
FlexCAN is transmitting and receiving CAN frames.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
24-47