PXR40RM Datasheet, PDF (403/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
Table 13-5. MMUCSR0 - MMU Control and Status Register 0
Field
Description
0–29
Reserved¹
30
TLB1_FI
31
TLB1 flash invalidate
0 - No flash invalidate
1 - TLB1 invalidation operation
When written to a ‘1’, a TLB1 invalidation operation is initiated by hardware. Once
complete, this bit is reset to ‘0’. Writing a ‘1’ while an invalidation operation is in
progress will result in an undefined operation. Writing a ‘0’ to this bit while an
invalidation operation is in progress will be ignored. TLB1 invalidation operations
require 3 cycles to complete.
Reserved¹
1 _{These bits are not implemented, will be read as zero, and writes are ignored.}
13.4.5.3 MMU Assist Registers (MAS)
The PXR40 uses special purpose registers (MAS0, MAS1, MAS2, MAS3, MAS4 and MAS6) to facilitate
reading and writing the TLBs. The MAS registers can be read or written using the mfspr and mtspr
instructions.
The MAS0 register is shown below.
0
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 624; Read/ Write; Reset - Unaffected
Figure 13-7. MMU Assist Register 0 (MAS0)
Fields are defined below.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-15