PXR40RM Datasheet, PDF (1252/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
Table 29-21. Longest Threads and RAM Accesses for old TPU Functions (continued)
Function
Longest Thread RAM Accesses
SPWM
Mode 0
14
4
Mode1
18
4
Mode 2
20 (no linking)
4
22 (linking
4
PMA
94
8
PMM
94
8
PSP
Angle-Angle Mode
76
6
Angle-Time Mode
50
3
1
SM
160
21
PPWA
Mode 0
44₂
9
Mode 1
50
10
Mode 2
44
9
Mode 3
50
10
1 _{Assumes one master and one slave. For each}
additional slave
a) Add 32 clocks and 2 RAM accesses, and
b) Add (STEP_RATE_CNT  two clocks)
2 _{With one channel linked. Add two clocks for each}
additional channel linked.
Mapping the Channels for Each Time Slot
To determine when a channel will be serviced again, it is necessary to determine which other channels will
be serviced first. Do this by assuming all channels are continuously requesting service and mapping the
channels into the time-slot sequence.
Adding Time for Time-Slot Transitions
Add six eTPU clocks for time-slot transitions which occur after each time slot.
29.4.2.4.2 First-Pass Analysis Worst-Case Latency Examples
The examples in this section assume the system configuration shown in Table 29-22.
Table 29-22. System Configuration Example
Channel Priority
Function^{1, 2}
0
High
PWM (driving a DC motor)
1
Middle PPWA (Mode 0, measuring the DC motor speed)
2
Low
DIO (Input)
1 _{9% RAM Collision Rate (RCR)}
2 _{CPU clock rate = 40 MHz, or 25 ns per clock period}
29-84
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor