PXR40RM Datasheet, PDF (252/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
Table 7-45. SIU_SYSDIV Bit Field Descriptions
Field
Description
24–26
27
BYPASS
28–29
SYSCLKDIV
30–31
Reserved
Bypass bit.
0 system clock divider is not bypassed
1 system clock divider is bypassed
System Clock Divider. The SYSCLKDIV bits select the divider value for the system clock. Note that
the SYSCLKDIV divider is required in addition to the RFD to allow the other source for the system
clock (OSC) to be divided down to slowest frequencies to improve power. The output of the clock
divider is nominally a 50% duty cycle.
00 Divide by 2
01 Divide by 4
10 Divide by 8
11 Divide by 16
Reserved
7.3.1.28 Halt Register (SIU_HLT)
The SIU_HLT register is used to disable the clocks to various modules. Each bit will drive a separate stop
output of the SIU. These outputs will be connected as shown in Table 7-46.
NOTE
Some peripherals have an MDIS (module disable) bit in the module control
register that can be set to disable the module clock, reducing power
consumption. In most cases the peripheral registers are still readable and
writeable. However, using the SIU_HLT register also disables the read/write
functions on the disabled peripheral's registers for additional power saving.
See Section Chapter 20, Periodic Interrupt Timer (PIT_RTI), for more
information on how to use the SIU_HLT and SIU_HLTACK registers.
Address: SIU_BASE + 0x9A4
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
HLT
W
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
HLT
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 7-26. Halt Register (SIU_HLT)
7-70
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor