PXR40RM Datasheet, PDF (1005/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Address: 0x0064
0
1
2
3
4
5
6
78
R
0
0
NCIE2 TORIE2 PIE2 EOQIE2 CFUIE2
CFFE2 CFFS2
W
Reset 0
0
0
0
0
0
0
00
Access: User read/write
9 10 11 12 13 14
15
000
0
RFOIE2 RFDE2 RFDS2
000 0 0 0
0
16
17
18
19
20 21 22
23 24 25 26 27 28 29 30
31
R
0
0000
0
NCIE3 TORIE3 PIE3 EOQIE3 CFUIE3
CFFE3 CFFS3
RFOIE3 RFDE3 RFDS3
W
Reset 0
0
0
0
0
0
0
0 0000 0 0 0
0
Figure 27-9. EQADC Interrupt and DMA Control Register 1 (EQADC_IDCR1)
Address: 0x0068
0
1
2
3
4
5
6
78
R
0
0
NCIE4 TORIE4 PIE4 EOQIE4 CFUIE4
CFFE4 CFFS4
W
Reset 0
0
0
0
0
0
0
00
Access: User read/write
9 10 11 12 13 14
15
000
0
RFOIE4 RFDE4 RFDS4
000 0 0 0
0
16
17
18
19
20 21 22
23 24 25 26 27 28 29 30
31
R
0
0000
0
NCIE5 TORIE5 PIE5 EOQIE5 CFUIE5
CFFE5 CFFS5
RFOIE5 RFDE5 RFDS5
W
Reset 0
0
0
0
0
0
0
0 0000 0 0 0
0
Figure 27-10. EQADC Interrupt and DMA Control Register 2 (EQADC_IDCR2)
Table 27-11. EQADC_IDCR Field Description
Field
Description
0
16
NCIEx
1
17
TORIEx
2
18
PIEx
Non-Coherency Interrupt Enable x. NCIEx enables the EQADC to generate an interrupt request when the
corresponding EQADC_FISR[NCFx] is asserted.
0 Disable non-coherency interrupt request.
1 Enable non-coherency interrupt request.
Trigger Overrun Interrupt Enable x. TORIEx enables the EQADC to generate an interrupt request when the
corresponding EQADC_FISR[TORFx] is asserted.
Apart from generating an independent interrupt request for a CFIFOx Trigger Overrun event, the EQADC also
provides a combined interrupt at which the Result FIFO Overflow Interrupt, the Command FIFO Underflow
Interrupt, and the Command FIFO Trigger Overrun Interrupt requests of ALL CFIFOs are ORed. When RFOIEx,
CFUIEx, and TORIEx are all asserted, this combined interrupt request is asserted whenever one of the following
18 flags becomes asserted: RFOFx, CFUFx, and TORFx (assuming that all interrupts are enabled). See
Section 27.7.8, EQADC DMA/Interrupt Request, for details.
0 Disable trigger overrun interrupt request.
1 Enable trigger overrun interrupt request.
Pause Interrupt Enable x. PIEx enables the EQADC to generate an interrupt request when the corresponding
EQADC_FISR[PFx] is asserted.
1 Enable pause interrupt request.
0 Disable pause interrupt request.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-23