PXR40RM Datasheet, PDF (1305/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
D_CLKOUT
BB
D_ADD[9:30]
Slave 1
*
Slave 2
*
D_RD_WR
D_TS
**
D_ADD_DAT[0:31]
D_TA, D_TEA
Slave 1
allowed to
drive
acknowledge
signals
Slave 1
negates
acknowledge
signals and
‘turns off’
Slave 2
allowed to
drive
acknowledge
signals
Slave 2
negates
acknowledge
signals and
‘turns off’
* The EBI drives address and control signals an extra cycle because it uses a latched version of D_TA
(1 cycle delayed) to terminate the cycle. An external master is not required to do this.
** This is the earliest that the EBI can start another transfer, in the case of continuing a set of small accesses.
For all other cases, an extra cycle is needed before the EBI can start another D_TS.
Figure 30-33. Termination Signals Protocol Timing Diagram
30.4.2.9 Non-Chip-Select Burst in 16-bit Data Bus Mode
The timing diagrams in this section apply only to the special case of a non-chip-select 32-bit access in
16-bit data bus mode (DBM=1 in EBI_MCR).
For this case, a special 2-beat burst protocol is used for reads and writes, so that a slave device (using the
same EBI) can internally generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two
separate 16-bit accesses.
NOTE
Since this device does not support multi-master systems, the original intent
of this protocol does not apply. However, this 2-beat burst protocol can also
occur in a single-master system, if a non-chip-select 32-bit access to a 16-bit
port is performed.
Figure 30-34 shows a 32-bit non-chip-select read from an external master in 16-bit data bus mode.
Figure 30-35 shows a 32-bit non-chip-select write from an external master in 16-bit data bus mode.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
30-43