PXR40RM Datasheet, PDF (856/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexCAN Module
24.4.9.2 Module Disable Mode
This low power mode is entered when the MDIS bit in the FLEXCAN_x_MCR Register is asserted. If the
FlexCAN module is disabled during Freeze Mode, the module sends a request to disable the clocks to the
CAN Protocol Interface (CPI) and Message Buffer Management (MBM) sub-modules, sets the
MDISACK bit and negates the FRZ_ACK bit. If the module is disabled during transmission or reception,
FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and then
checks it to be recessive
• Waits for all internal activities like arbitration, matching, move-in and move-out to finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the CPI and MBM sub-modules
• Sets the NOT_RDY and MDISACK bits in FLEXCAN_x_MCR
The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped registers, except
the Free Running Timer, the Error Counter Register and the Message Buffers, which cannot be accessed
when the module is in Disable Mode. Exiting from this mode is done by negating the MDIS bit, which will
resume the clocks and negate the MDISACK bit.
24.4.9.3 Stop Mode
This is a system low power mode in which all MCU clocks are stopped for maximum power savings. If
FlexCAN receives the global Stop Mode request during Freeze Mode, it sets the MDISACK bit, negates
the FRZ_ACK bit and then sends a Stop Acknowledge signal to the CPU, in order to shut down the clocks
globally. If Stop Mode is requested during transmission or reception, FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and checks
it to be recessive
• Waits for all internal activities like arbitration, matching, move-in and move-out to finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Sets the NOT_RDY and MDISACK bits in FLEXCAN_x_MCR
• Sends a Stop Acknowledge signal to the CPU, so that it can shut down the clocks globally
Exiting Stop Mode is done by CPU resuming the clocks and removing the Stop Mode request.
24.4.10 Interrupts
The module can generate up to 69 interrupt sources (64 interrupts due to message buffers and 5 interrupts
due to ORed interrupts from MBs, Bus Off, Error, Tx Warning, and Rx Warning). The number of actual
sources depends on the configured number of Message Buffers.
Each one of the message buffers can be an interrupt source, if its corresponding IMASK bit is set. There
is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer
is initialized for either transmission or reception. Each of the buffers has assigned a flag bit in the IFLAG
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor