PXR40RM Datasheet, PDF (832/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexCAN Module
24.3.4.4 Rx Global Mask (FLEXCAN_x_RXGMASK)
This register is provided for legacy support. Setting the MBFEN bit in FLEXCAN_x_MCR causes the
FLEXCAN_x_RXGMASK Register to have no effect on the module operation.
FLEXCAN_x_RXGMASK is used as acceptance mask for all Rx MBs, excluding MBs 14–15, which have
individual mask registers. When the FEN bit in FLEXCAN_x_MCR is set (FIFO enabled), the
FLEXCAN_x_RXGMASK also applies to all elements of the ID filter table, except elements 6-7, which
have individual masks.
The contents of this register must be programmed while the module is in Freeze Mode, and must not be
modified when the module is transmitting or receiving frames.
Base + 0x0010
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R _{MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16}
W
RESET: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _{MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0}
W
RESET: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
= Unimplemented or Reserved
Figure 24-8. Rx Global Mask Register (FLEXCAN_x_RXGMASK)
Table 24-11. FLEXCAN_x_RXGMASK Field Descriptions
Field
Description
0–31 Mask Bits
MI31–MI0 For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the mask bits affect
all bits programmed in the filter table (ID, IDE, RTR).
0 The corresponding bit in the filter is “don’t care”
1 The corresponding bit in the filter is checked against the one received
24.3.4.5 Rx 14 Mask (FLEXCAN_x_RX14MASK)
This register is provided for legacy support. Setting the MBFEN bit in FLEXCAN_x_MCR causes the
FLEXCAN_x_RX14MASK Register to have no effect on the module operation.
FLEXCAN_x_RX14MASK is used as acceptance mask for the Identifier in Message Buffer 14. When the
FEN bit in FLEXCAN_x_MCR is set (FIFO enabled), the RXG14MASK also applies to element 6 of the
ID filter table. This register has the same structure as the Rx Global Mask Register. It must be programmed
while the module is in Freeze Mode, and must not be modified when the module is transmitting or
receiving frames.
• Address Offset: 0x14
• Reset Value: 0xFFFF_FFFF
24-22
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor