PXR40RM Datasheet, PDF (665/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
SADR_MBDF[n]
SADR_MBDF[i]
(min) RFDSR[ENTRY_SIZE] * 2 bytes
Frame Data[n]
Frame Data[i]
SADR_MBDF[1]
Frame Data[1]
Message Buffer Data Fields
SADR_MBHF[n]
+
Frame Header[n]
SADR_MBHF[i]
Frame Header[i]
Data Field Offset[n] Slot Status[n]
Data Field Offset[i] Slot Status[i]
SADR_MBHF[1]
Frame Header[1]
Data Field Offset[1] Slot Status[1]
Message Buffer Header Fields
RFDSR[A]
RFDSR[B]
RFSIR[A]
RFSIR[B]
RFARIR
RFBRIR
Receive FIFO Control Register
Figure 22-106. Receive FIFO Structure
22.6.3.4 Message Buffer Configuration and Control Data
This section describes the configuration and control data for each message buffer type.
22.6.3.4.1 Individual Message Buffer Configuration Data
Before an individual message buffer can be used for transmission or reception, it must be configured.
There is a set of common configuration parameters that applies to all individual message buffers and a set
of configuration parameters that applies to each message buffer individually.
Common Configuration Data
The set of common configuration data for individual message buffers is located in the following registers.
• Message Buffer Data Size Register (MBDSR)
The MBSEG2DS and MBSEG1DS fields define the minimum length of the message buffer data
field with respect to the message buffer segment.
• Message Buffer Segment Size and Utilization Register (MBSSUTR)
The LAST_MB_SEG1 and LAST_MB_UTIL fields define the segmentation of the individual
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-81