PXR40RM Datasheet, PDF (152/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Power Management Controller (PMC)
5.5.8 Trimming
During Power Up and Reset, the BandGap is untrimmed. This allows the MCU to come out of reset.
At the end of the Reset sequence, the BandGap is trimmed by the PMC. This trimming controls the
BandGap voltage, which is used as the reference for the Internal Regulators and LVD.
The BandGap Trim values are not visible and they cannot be altered or overwritten by the user.
The levels of the internal regulators and LVD, though, can be adjusted by the user by programming the
Trim Registers. This allows the user to control the internal regulator or LVD level within a range of +/- 8
steps from the default value. This is described in Section 5.4.2, Trimming Register (PMC_TRIMR).
5.5.9 Interrupts
The PMC generates one interrupt request signal for each LVD source: VDDREG LVD, VDDSYN LVD,
VDD LVD, and VDDA1 LVD. The module also generates combined interrupt request signal which is
asserted whenever any of the individual interrupt request signals becomes asserted.
5.5.10 PMC Power-on Reset
A Power-on reset (POR) circuit monitors its supply voltage, providing a logic reset in a guaranteed low
voltage range.
Power-on reset will assert as soon as possible after the voltage levels of the POR power supplies begin to
rise. Each POR will negate before its power supply rises into the specified range. The behavior for each
POR during power supply ramping is shown in Figure 5-8.
Power-on reset (POR) circuits are present at the following power supplies:
• 5V supply of the PMC block and bandgap (VDDREG)
• 1.2V core supply VDD
The POR can be used to prevent critical circuit-like band gap reference or LVDs to operate when the
supply voltage is too low (output signals are out of specification). POR trip voltage tracks with technology
variations and it should be such that all circuits, that are disabled by its output, can at least work with
supplies down to POR level.
The dependence between POR and LVD on VDDREG is summarized in Figure 5-9. As shown, the LVD
will reach a consistent state before the POR actually releases the reset, avoiding false startup condition.
5-20
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor