PXR40RM Datasheet, PDF (1047/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
EQADC MAC unit using the 12-bit data result of the resolution adjustment and the calibration
constants GCC and OCC, or ALTGCC and ALTOCC - refer to Section 27.7.6.6, ADC Calibration
Feature, for details. Then, this 14-bit data is further formatted into a 16-bit format according to the
status of the FMT bit in conversion command of the standard configuration or FFMT bit in the
conversion command of the alternate configurations¹. When FMT/FFMT is asserted, the 14-bit
result data is reformatted to look as if it was measured against an imaginary ground at VREF/2 (the
MSB bit of the 14-bit result is inverted), and is sign-extended to a 16-bit format as in Figure 27-47.
When FMT/FFMT is negated, the EQADC zero-extends the 14-bit result data to a 16-bit format as
in Figure 27-48. Correspondence between the analog voltage in a channel and the calculated digital
values is shown in Table 27-37.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIGN_EXT
RESOLUTION ADJUSTED CONVERSION_RESULT (With inverted MSB bit)
ADC Result
Figure 27-47. ADC Result Format when FMT=1 (Right Justified Signed)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
00
RESOLUTION ADJUSTED CONVERSION_RESULT
ADC Result
Figure 27-48. ADC Result Format when FMT=0 (Right Justified Unsigned)
1. For simplicity, the following text will refer to FMT only, but when using alternate configurations, refer to Conversion
Command Format for Alternate Configurations.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-65