PXR40RM Datasheet, PDF (1369/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
31.14.6.3.3 Data Trace Windowing
Data write/read messages are enabled via the RWT1(2) field in the data trace control register (DTC) for
each DTM channel. Data trace windowing is achieved via the address range defined by the DTEA and
DTSA registers and by the RC1(2) field in the DTC. All e200z7 initiated read/write accesses which fall
inside or outside these address ranges, as programmed, are candidates to be traced.
31.14.6.3.4 Data Access/Instruction Access Data Tracing
The Nexus3 module is capable of tracing both instruction access data or data access data. Each trace
window can be configured for either type of data trace by setting the DI1(2) field within the data trace
control register for each DTM channel.
31.14.6.3.5
e200z7 Bus Cycle Special Cases
Table 31-28. e200z7 Bus Cycle Cases
Special Case
Action
e200z7 bus cycle aborted
Cycle ignored
e200z7 bus cycle with data error (TEA)
Data Trace Message discarded
e200z7 bus cycle completed without error
Cycle captured & transmitted
e200z7 bus cycle initiated by NZ7C3
Cycle ignored
e200z7 bus cycle is an instruction fetch
Cycle ignored
e200z7 bus cycle accesses misaligned data (across 64-bit 1st and 2nd cycle captured, and 2 DTM’s
boundary)—both 1st and 2nd transactions within data trace transmitted (see Note)
range
e200z7 bus cycle accesses misaligned data (across 64-bit 1st cycle captured and transmitted; 2nd cycle
boundary)—1st transaction within data trace range; 2nd ignored
transaction out of data trace range
e200z7 bus cycle accesses misaligned data (across 64-bit 1st cycle ignored; 2nd cycle capture and
boundary)—1st transaction out of data trace range; 2nd transmitted
transaction within data trace range
NOTE
For misaligned accesses (crossing 64-bit boundary), the access is broken
into two accesses. If both accesses are within the data trace range, two
DTMs are sent: one with a size encoding indicating the size of the original
access (a word), and one with a size encoding for the portion which crossed
the boundary (3 bytes).
NOTE
An STM to the cache’s store buffer within the data trace range initiates a
DTM message. If the corresponding memory access causes an error, a
checkstop condition occurs. The debug/development tool must use this
indication to invalidate the previous DTM.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31-53