PXR40RM Datasheet, PDF (925/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65536
Table 25-37. Delay Values
Delay Prescaler Values
1
20.0 ns
40.0 ns
80.0 ns
160.0 ns
320.0 ns
640.0 ns
1.3 s
2.6 s
5.1 s
10.2 s
20.5 s
41.0 s
81.9 s
163.8 s
327.7 s
655.4 s
3
60.0 ns
120.0 ns
240.0 ns
480.0 ns
960.0 ns
1.9 s
3.8 s
7.7 s
15.4 s
30.7 s
61.4 s
122.9 s
245.8 s
491.5 s
983.0 s
2.0 ms
5
100.0 ns
200.0 ns
400.0 ns
800.0 ns
1.6 s
3.2 s
6.4 s
12.8 s
25.6 s
51.2 s
102.4 s
204.8 s
409.6 s
819.2 s
1.6 ms
3.3 ms
7
140.0 ns
280.0 ns
560.0 ns
1.1 s
2.2 s
4.5 s
9.0 s
17.9 s
35.8 s
71.7 s
143.4 s
286.7 s
573.4 s
1.1 ms
2.3 ms
4.6 ms
25.5.4 Calculation of FIFO Pointer Addresses
The user has complete visibility of the TX and RX FIFO contents through the FIFO registers, and valid
entries can be identified through a memory mapped pointer and a memory mapped counter for each FIFO.
The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is
the Transmit Next Pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the Pop Next Pointer
(POPNXTPTR). Figure 25-42 illustrates the concept of first-in and last-in FIFO entries along with the
FIFO Counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
See Section 25.4.3.4, Transmit First In First Out (TX FIFO) Buffering Mechanism, and Section 25.4.3.5,
Receive First In First Out (RX FIFO) Buffering Mechanism, for details on the FIFO operation.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-65