PXR40RM Datasheet, PDF (1157/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
Table 28-17. eQADC Alternate Configuration Selection
ALT_CONFIG_SEL[0:7]
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Alternate Configuration
Alternate Configuration Not Used
1
2
3
4
5
6
7
8
Each eQADC alternate configuration uses the format specified in Figure 28-21. The RET_INH, DEST,
and FMTA bits/fields in the Alternate Configuration register pertain to Decimation Filter operation, and
the RESSEL and PRE_GAIN fields do not. The RET_INH bit is used by eQADC to set the Decimation
Filter in/out of prefill mode. The DEST field determines which Decimation Filter the conversion result is
sent to, and the encoding is given in Table 28-18. The FMTA bit determines whether the data going to the
Decimation Filter is signed or unsigned.
The eight Alternate Configurations are stored in the ADC by executing write commands to the On-Chip
ADC Alternate Configuration Registers. The write command is specified in the Write Configuration
Command Format for On-Chip ADC Operation section of the reference manual. The Alternate
Configuration register addresses 0x30 through 0x4C for each ADC0/1 converter in an eQADC are given
at the top of the register diagram.
ADC0/1 Register Address: 0x30, 0x34, 0x38, 0x3C, 0x40, 0x44, 0x48, 0x4C
Access: User read only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{RET_} 0
W ^INH
DEST
0
0
0
0
0
FMTA
RESSEL
PRE_GAIN
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28-21. Alternate Configuration 1-8 Control Registers (ADC_ACR1-8)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-43