PXR40RM Datasheet, PDF (729/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
22.6.20.1.2 FIFO Interrupts
The controller provides 2 FIFO interrupt sources.
Each of the 2 FIFO provides a Receive FIFO Almost Full Interrupt Flag. The controller sets the Receive
FIFO Almost Full Interrupt Flags (GIFER.FAFBIF, GIFER.FAFAIF) in the Global Interrupt Flag and
Enable Register (GIFER) if the corresponding Receive FIFO fill level exceeds the defined watermark.
22.6.20.1.3 Wakeup Interrupt
The controller provides one interrupt source related to the wakeup.
The controller sets the Wakeup Interrupt Flag GIFER.WUPIF when it has received a wakeup symbol on
the FlexRay bus. The controller generates an interrupt request if the interrupt enable bit GIFER.WUPIE is
asserted.
22.6.20.1.4 Protocol Interrupts
The controller provides 25 interrupt sources for protocol related events. For details, see Protocol Interrupt
Flag Register 0 (PIFR0) and Protocol Interrupt Flag Register 1 (PIFR1). Each interrupt source has its own
interrupt enable bit.
22.6.20.1.5 CHI Error Interrupts
The controller provides 16 interrupt sources for CHI related error events. For details, see CHI Error Flag
Register (CHIERFR). There is one common interrupt enable bit GIFER.CHIIE for all CHI error interrupt
sources.
22.6.20.2 Combined Interrupt Sources
Each combined interrupt source generates an interrupt request only when at least one of the interrupt
sources that is combined generates an interrupt request.
22.6.20.2.1 Receive Message Buffer Interrupt
The combined receive message buffer interrupt request RBIRQ is generated when at least one of the
individual receive message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable bit
GIFER.RBIE is set.
22.6.20.2.2 Transmit Message Buffer Interrupt
The combined transmit message buffer interrupt request TBIRQ is generated when at least one of the
individual transmit message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable
bit GIFER.TBIE is asserted.
22.6.20.2.3 Protocol Interrupt
The combined protocol interrupt request PRTIRQ is generated when at least one of the individual protocol
interrupt sources generates an interrupt request and the interrupt enable bit GIFER.PRIE is set.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-145