PXR40RM Datasheet, PDF (264/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
SIU_BASE + 0xD54
R
W
RESET:
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
11 10 9
8
6
5
4
3
2
1
0 23 15 14 13 12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
23 15 14 13 12 11 10 9
8
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-37. eMIOS Select Register for DSPI_B (SIU_EMIOSB)
Table 7-58. SIU_EMIOSB Field Descriptions
Field
Description
0–31
EMIOS channel select
EMIOSx 0 This bit in the DSPI_B serialized output frame will not use the respective EMIOS channel
1 This bit in the DSPI_B serialized output frame will use the respective EMIOS channel
SIU_BASE + 0xD58
R
W
RESET:
0
DSPI
BH
0
0
1
DSPI
BH
1
0
2
DSPI
BH
2
0
3
DSPI
BH
3
0
4
DSPI
BH
4
0
5
DSPI
BH
5
0
6
DSPI
BH
6
0
7
DSPI
BH
7
0
8
DSPI
BH
8
0
9
DSPI
BH
9
0
10
DSPI
BH
10
0
11
DSPI
BH
11
0
12
DSPI
BH
12
0
13
DSPI
BH
13
0
14
DSPI
BH
14
0
15
DSPI
BH
15
0
R
W
RESET:
16
DSPI
BL
16
0
17
DSPI
BL
17
0
18
DSPI
BL
18
0
19
DSPI
BL
19
0
20
DSPI
BL
20
0
21
DSPI
BL
21
0
22
DSPI
BL
22
0
23
DSPI
BL
23
0
24
DSPI
BL
24
0
25
DSPI
BL
25
0
26
DSPI
BL
26
0
27
DSPI
BL
27
0
28
DSPI
BL
28
0
29
DSPI
BL
29
0
30
DSPI
BL
30
0
31
DSPI
BL
31
0
Figure 7-38. SIU_DSPIBH/L Select Register for DSPI_B (SIU_DSPIBHLB)
Table 7-59. SIU_DSPIBHLB Field Descriptions
Field
Description
0–31
DSPI_B Data Register bit
DSPIBH/Lx 0 The corresponding serial GPO B output (from the SIU_DSPIBH/L register) is disabled
1 The corresponding serial GPO B output (from the SIU_DSPIBH/L register) is enabled
7.3.1.33.4 Serialized Output Signal Selection Registers for DSPI_C
The following three registers are used by DSPI_C to select the sources of the serialized output when
running in DSI or CSI configuration.
Each register bit enables a path from the eTPU_A channel, eMIOS channel and data register bit
SIU_DSPICH/SIU_DSPICL to the equivalent bit position in the DSPI_C serialized output frame. The user
must ensure that bit selections from each of these registers do not overlap. Multiple sources are logically
ORed, which provides the potential for combining outputs from multiple timer channels and data registers
to produce more complex bit behavior.
7-82
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor