PXR40RM Datasheet, PDF (1415/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Device Performance Optimization
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0
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1013; Read/Write; Reset - 0x0
Figure 33-1. Branch Unit Control & Status Register (BUCSR)
Table 33-1. BUCSR Register Field Descriptions
Field
0–21
22
BBFI
23–25
26–27
BALLOC
28
29–30
BPRED
Description
Reserved
Branch target buffer flash invalidate. When set, BBFI flash clears the valid bit of all BTB entries; clearing occurs
regardless of the value of the enable bit (BPEN).
Note: BBFI is always read as 0.
Reserved
Branch Target Buffer Allocation Control
00- Branch Target Buffer allocation for all branches is enabled.
01- Branch Target Buffer allocation is disabled for backward branches.
10- Branch Target Buffer allocation is disabled for forward branches.
11- Branch Target Buffer allocation is disabled for both branch directions.
This field controls BTB allocation for branch acceleration when BPEN=1. Note that BTB hits are not affected by
the settings of this field. Note that for branches with“AA’=‘1’, the MSB of the displacement field is still used to
indicate forward/backward, even though the branch is absolute.
Reserved
Branch Prediction Control (Static)
00- Branch predicted taken on BTB miss for all branches.
01- Branch predicted taken on BTB miss only for forward branches.
10- Branch predicted taken on BTB miss only for backward branches.
11- Branch predicted not taken on BTB miss for both branch directions.
This field controls operation of static prediction mechanism on a BTB miss. Unless disabled, fetching of the
predicted target location will be performed for branch acceleration. BPRED operates independently of BPEN, and
with a BPEN setting of 0, will be used to perform static prediction of all unresolved branches.
31
BPEN
Note that BTB hits are not affected by the settings of this field. Note that for certain applications, setting BPRED
to a non-default value may result in improved performance.
Branch target buffer (BTB) enable.
0 BTB prediction disabled. No hits are generated from the BTB and no new entries are allocated. Entries are
not automatically invalidated when BPEN is cleared; BBFI controls entry invalidation.
1 BTB prediction enabled (enables BTB to predict branches).
Further details of the BUCSR register can be found in the e200z7 Reference Manual.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
33-3