PXR40RM Datasheet, PDF (1292/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
D_CLKOUT
D_ADD[9:30]
D_RD_WR
D_BDIP
D_TS
D_ADD_DAT[0:31]
D_ADD_DAT is valid
D_TA
CSx
D_ADD_DAT is valid
D_WE
Figure 30-21. Read After Write to the Same CS Bank
30.4.2.5 Burst Transfer
The EBI supports wrapping 32-byte critical-doubleword-first burst transfers. Bursting is supported only
for internally-requested cache-line size (32-byte) read accesses to external devices that use the chip
selects¹.
Accesses to devices operating without a chip select are always single beat. If an internal request to the EBI
indicates a size of less than 32 bytes, the request is fulfilled by running one or more single-beat external
transfers, not by an external burst transfer.
An 8-word wrapping burst reads eight 32-bit words by supplying a starting address that points to one of
the words (doubleword aligned) and requiring the memory device to sequentially drive each word on the
data bus. The selected slave device must internally increment D_ADD[27:29] (also D_ADD30 in the case
of a 16-bit port size device) of the supplied address for each transfer, until the address reaches an 8-word
boundary, and then wrap the address to the beginning of the 8-word boundary. The address and transfer
attributes supplied by the EBI remain stable during the transfers. Termination of each beat transfer occurs
by the EBI asserting D_TA (SETA=1 is not supported for burst transfers). The EBI requires that addresses
be aligned to a doubleword boundary on all burst cycles.
Table 30-13 shows the burst order of beats returned for an 8-word burst to a 32-bit port.
1. Except for the special case of a 32-bit non-chip-select access in 16-bit data bus mode. See Section 30.4.2.9,
Non-Chip-Select Burst in 16-bit Data Bus Mode.
30-30
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor