PXR40RM Datasheet, PDF (174/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Feedback count does not
equal reference count of N or
N+K. Alert system that PLL
is not locked. Tighten
lock criteria.
Continue
monitoring PLL
with alternate
N and N+K count
and compare
sequences.
Alert system that
PLL has locked.
Count N
reference cycles,
and compare
number of feedback
cycles elapsed.
Lock detected
Relax lock
criteria.
Reference count
equals N and feed-
back count equals N
in same count and
compare sequence.
Count N + K
Reference cycles,
and compare
number of feed-
back cycles
elapsed.
Reference count
equals N + K and feed-
back count equals N + K
in same count and
compare sequence.
Figure 6-7. Lock Detect Sequence
After the PLL acquires lock after reset, the LOCK and LOCKS status bits are set. If the EPREDIV or
EMFD are changed, or if an unexpected loss-of-lock condition occurs, the LOCK and LOCKS status bits
are negated. While the PLL is in an unlocked condition, the system clocks continue to be sourced from the
PLL as the PLL attempts to re-lock. Consequently, during the re-locking process, the system clock
frequency is not well defined and may exceed the maximum system frequency violating the system clock
timing specifications. Because of this condition, use of the loss-of-lock reset function is recommended.
After the PLL has re-locked, the LOCK bit is set. The LOCKS bit remains cleared if the loss of lock was
unexpected. The LOCKS bit is set to one when the loss of lock was caused by changing the EPREDIV or
EMFD fields.
6.4.3.2 Loss-of-Clock Detection
When enabled by the LOCEN bit in the ESYNCR2, the loss-of-clock (LOC) detection circuit monitors the
input clocks to the phase/frequency detector (PFD) (see Figure 6-2). When the reference or feedback clock
frequency falls below a minimum frequency, the LOC circuitry considers the clock to have failed and a
loss-of-clock status is reflected by the sticky LOCF bit, and non-sticky LOC bit in the SYNSR. See PXR40
Microcontroller Data Sheet for the minimum clock frequency. In PLL Off mode, the loss-of-clock
circuitry is disabled.
Depending which clock source has failed, the LOC circuitry switches the PLL output clock’s source to the
remaining operational clock if enabled by LOCEN. The PLL output clocks are derived from the alternate
clock source until reset is asserted. The alternate clock source used is dependent on whether the LOC is
6-16
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor