PXR40RM Datasheet, PDF (376/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Flash Memory Array and Control
NOTE
A reset value of 1* in Figure 12-13 indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
Offset: 0x0024
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
LBCFG
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1*
Figure 12-13. Flash Bus Interface Configuration Register 2 (FLASH_BIUCR2)
12.2.2.11 User Test Register 0 (FLASH_x_UT0)
The User Test Register 0 (FLASH_x_UT0) provides a means to control UTest. The UTest mode gives the
users of the flash module the ability to perform test features on the flash. This register is only writable
when the flash is put into UTest mode by writing a passcode.
Offset: 0x003C / 0x403C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
UTE SCBE
DSI
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
AID
EA
MRE MRV EIE AIS AIE
W
Reset 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
Figure 12-14. User Test Register 0 (FLASH_x_UT0)
12-24
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor