PXR40RM Datasheet, PDF (859/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexCAN Module
• Initialize the Message Buffers
– The Control and Status word of all Message Buffers must be initialized
– If FIFO was enabled, the 8-entry ID table must be initialized
– Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in
FLEXCAN_x_CTRL Register (for Bus Off and Error interrupts)
• Negate the HALT bit in FLEXCAN_x_MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
24.5.2 FlexCAN Addressing and RAM size configurations
There are 3 RAM configurations that can be implemented within the FlexCAN module. The possible
configurations are:
• For 16 MBs: 288 bytes for MB memory and 64 bytes for Individual Mask Registers
• For 32 MBs: 544 bytes for MB memory and 128 bytes for Individual Mask Registers
In each configuration the user can program the maximum number of MBs that will take part in the
matching and arbitration processes using the MAXMB field in the FLEXCAN_x_MCR Register. For 16
MB configuration, MAXMB can be any number between 0–15.For 32 MB configuration, MAXMB can
be any number between 0–31.For 64 MB configuration, MAXMB can be any number between 0–63.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
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