PXR40RM Datasheet, PDF (441/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

14.3 Functional Description
This section describes the functionality of the XBAR in more detail.
AMBA Crossbar Switch (XBAR)
14.3.1 Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep
arbitration delays to a minimum.
This section examines data throughput from the point of view of masters and slaves, detailing when the
XBAR stalls masters, or inserts bubbles on the slave side.
14.3.2 General Operation
When a master makes an access to the XBAR from an idle master state, the access is taken immediately
by the XBAR. If the targeted slave port of the access is available (that is, the requesting master is currently
granted ownership of the slave port), the access is immediately presented on the slave port. It is possible
to make single clock (zero wait state) accesses through the XBAR by a granted master. If the targeted slave
port of the access is busy or parked on a different master port, the requesting master receives wait states
until the targeted slave port can service the master request. The latency in servicing the request depends
on each master’s priority level and the responding slave’s access time.
Because the XBAR appears to be simply another slave to the master device, the master device has no
indication that it owns the slave port it is targeting. While the master does not have control of the slave port
it is targeting, it is wait-stated.
A master is given control of a targeted slave port only after a previous access to a different slave port has
completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from
occurring when a master has the following conditions:
• Outstanding request to slave port A that has a long response time
• Pending access to a different slave port B
• Lower priority master also makes a request to the different slave port B.
In this case, the lower priority master is granted bus ownership of slave port B after a cycle of arbitration,
assuming the higher priority master slave port A access is not terminated.
After a master has control of the slave port it is targeting, the master remains in control of that slave port
until it gives up the slave port by running an IDLE cycle, leaves that slave port for its next access, or loses
control of the slave port to a higher priority master with a request to the same slave port. However, because
all masters run a fixed-length burst transfer to a slave port, it retains control of the slave port until that
transfer sequence is completed. In round-robin arbitration mode, the current master is forced to hand off
bus ownership to an alternately requesting master at the end of its current transfer sequence.
When a slave bus is idled by the XBAR, it can be parked on the master port using the PARK bits in the
XBAR_SGPCR (slave general-purpose control register), or on the last master to have control of the slave
port. This can avoid the initial clock of the arbitration delay if the master must arbitrate to gain control of
the slave port. The slave port can also be put into low-power park mode to save power.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
14-9