PXR40RM Datasheet, PDF (62/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Introduction
— Reduced-pin JTAG mode as per IEEE 1149.7
• Host processor (e200z7) standard class 3 compliant
• eTPU development support standard class 3 compliant
• Supports data trace for the FlexRay controller and both eDMA2 modules
• Run-time access to the on-chip memory map via the Nexus read/write access protocol
• All features are independently configurable and controllable via the IEEE 1149.1 I/O port
• The NDI block reset is controlled with JCOMP, power-on reset, and the TAP state machine. All
these sources are independent of system reset.
• Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
1.3 Developer Environment
The PXR40 supports several tools to enable easier application development.
The following development support will be available.
• Tower system modules for evaluation and prototyping
• Compilers
• Debuggers
• JTAG and Nexus interfaces
• RAppID™ Initialization tool
1-22
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor