PXR40RM Datasheet, PDF (197/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
7.3.1.3 System Reset Control Register (SIU_SRCR)
The system reset control register configures whether a software system reset or a software external reset
is generated. An software system reset uses an internal system reset. An software external reset asserts
RSTOUT.
Address: SIU_BASE + 0x0010
Access: R/W
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R 0 SER 0
0
0
0
0
0
0
0
0
0
0
0
0
0
W _SSR1
see
note²
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 _{The SSR bit always reads 0. A write of 0 to this bit has no effect.}
2 _{Write 1 to the SER bit to generate a software external reset. A write of 0 to this bit has no effect. When the reset completes,}
the SER bit is cleared to 0.
Figure 7-4. System Reset Control Register (SIU_SRCR)
The following table describes the fields in the system reset control register:
Table 7-10. SIU_SRCR Bit Field Descriptions
Field
0
SSR
Description
Software system reset.
The software system reset is processed as a synchronous reset. Except for a software external reset, the bit
automatically clears if any other reset source asserts.
1
SER
0 No software system reset.
1 Generate an software internal system reset.
Software external reset. Used to generate a software external reset. Writing a 1 to this bit asserts RSTOUT for 2400
clocks, and the internal reset is not asserted. The bit automatically clears when the software external reset
completes or any other reset source is asserted. After a software external reset has been initiated, RSTOUT negates
if this bit is cleared before the 2400 clock period expires.
2–31
0 Do not generate a software external reset.
1 Generate a software external reset.
Reserved
7.3.1.4 External Interrupt Status Register (SIU_EISR)
The external interrupt status register is used to record edge-triggered events on the IRQ[0]–IRQ[15] inputs
to the SIU and record the critical interrupts NMI and SWT. When an edge-detect enable bit is set in the
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-15