PXR40RM Datasheet, PDF (751/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
23.3.2.5 eMIOS200 B Register (EMIOS_CBDR[n])
Offset: UC[n] base address + 0x0004
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
W
B[0:23]
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
B[0:23]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-6. eMIOS200 B Register (EMIOS_CBDR[n])
Depending on the mode of operation, internal registers B1 or B2 can be assigned to address
EMIOS_CBDR[n]. Both B1 and B2 are cleared by reset. Table 23-7 summarizes the EMIOS_CBDR
writing and reading accesses for all operation modes. For more information see section Section 23.4.1.1,
Unified Channel Modes of Operation.
Depending on the channel configuration, it may have the EMIOS_CBDR register or not. This means that
if at least one mode that requires the register is implemented, then the register is present. Otherwise, it is
absent. PXR40 has register B (EMIOS_CBDR) in all channels.
Table 23-7. EMIOS_CADR[n], EMIOS_CBDR[n], and EMIOS_ALTA[n] Values Assignment
Operation Mode
GPIO
SAIC¹
SAOC¹
IPWM
IPM
DAOC
PEA
PEC¹
QDEC¹
WPTA
MC¹
OPWFM
OPWMC
OPWM
MCB¹
Write
A1, A2
—
A2
—
—
A2
A1
A1
A1
A1
A2
A2
A2
A2
A2
Read
A1
A2
A1
A2
A2
A1
A2
A1
A1
A1
A1
A1
A1
A1
A1
Register Access
Write
B1, B2
B2
B2
—
—
B2
—
B1
B2
B1
B2
B2
B2
B2
B2
Read Alternate Write Alternate Read
B1
A2
A2
B2
—
—
B2
—
—
B1
—
—
B1
—
—
B1
—
—
B1
—
—
B1
—
A2
B2
—
—
B1
—
A2
B2
—
—
B1
—
—
B1
—
—
B1
—
—
B2
—
—
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-11