PXR40RM Datasheet, PDF (914/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCSx
t_CSC
t_ASC t_{DT tCSC}
t_CSC = PCS to SCK delay
t_ASC = After SCK delay
t_DT = Delay after Transfer (minimum CS negation time)
Figure 25-33. Example of Non-Continuous Format (CPHA=1, CONT=0)
When the CONT bit = 1, the PCS signal remains asserted for the duration of the two transfers. The Delay
between Transfers (t_DT) is not inserted between the transfers. Figure 25-34 shows the timing diagram for
two four-bit transfers with CPHA = 1 and CONT = 1.
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCS
t_CSC
t_CSC = PCS to SCK delay
t_ASC = After SCK delay
t_ASC t_CSC
Figure 25-34. Example of Continuous Transfer (CPHA=1, CONT=1)
Switching CTAR registers or changing which PCS signals are asserted between frames while using
Continuous Selection can cause errors in the transfer. The PCS signal should be negated before CTAR is
switched or different PCS signals are selected.
25-54
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor