PXR40RM Datasheet, PDF (377/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Flash Memory Array and Control
Field
0
UTE
1
SCBE
2–7
8–15
DSI
16–23
24
EA
25
26
MRE
27
MRV
28
EIE
29
AIS
Table 12-15. FLASH_x_UT0 Field Descriptions
Description
UTest Enable. This status bit gives indication when UTest is enabled. All bits in FLASH_x_UT0, FLASH_x_UT1,
FLASH_x_UT2 are locked when this bit is 0. This bit is not writeable to a 1, but may be cleared. The reset value
is 0. The method to set this bit is to provide a password, and if the password matches, the UTE bit is set to reflect
the status of enabled, and is enabled until it is cleared by a register write. The UTE password will only be
accepted if FLASH_x_MCR[PGM] = 0 and FLASH_x_MCR [ERS] = 0 (program and erase are not being
requested). UTE can only be cleared if FLASH_x_UT0[AID] = 1, FLASH_x_UT0[AIE] and
FLASH_x_UT0[EIE] = 0. While clearing UTE, writes to set AIE or set EIE will be ignored. For UTE, the password
0xF9F9_9999 must be written to the FLASH_x_UT0 register.
Single Bit Correction Enable. SBC enables Single Bit Correction results to be observed in FLASH_x_MCR[SBC].
Also is used as an enable for interrupt signals created by the c90fl module (see c90fl Integration Guide). ECC
corrections that occur when SBCE is cleared will not be logged.
0 Single Bit Corrections observation is disabled.
1 Single Bit Correction observation is enabled.
Reserved
Data Syndrome Input. These bits enable checks of ECC logic by allowing check bits to be input into the ECC
logic and then read out by doing array reads or array integrity checks. The DSI[7:0] correspond to the 8 ECC
check bits on a double word.
Reserved
ECC Algorithm. EA is a status bit that provides information about the ECC algorithm used within the Flash. Either
a modified Hamming code is used, or a modified Hsiao code is used.
0 ECC is implemented with a modified Hamming algorithm.
1 ECC is implemented with a modified Hsiao algorithm.
Reserved
Margin Read Enable. MRE combined with MRV enables Factory Margin Reads to be done. Margin reads are only
active during Array Integrity Checks. Normal user reads are not affected by MRE. MRE is not writable if AID is low.
0 Margin reads are not enabled.
1 Margin reads are enabled during Array Integrity Checks.
Margin Read Value. MRV selects the margin level that is being checked. Margin can be checked to an erased
level (MRV = 1) or to a programmed level (MRV = 0). In order for this value to be valid, MRE must also be set.
MRV is not writable if AID is low.
0 Zero’s margin reads are requested.
1 One’s margin reads are requested.
ECC Data Input Enable. EIE enables the input registers (DSI and DAI) to be the source of data for the array. This
is useful in the ECC logic check. If this bit is set, data read through a BIU read request will be from the DSI and
DAI registers when an address match is achieved to the FLASH_x_AR. EIE is not simultaneously writable to a 1
as UTI is being cleared to a 0.
0 Data read is from the flash array.
1 Data read is from the DSI and DAI registers.
Array Integrity Sequence. AIS determines the address sequence to be used during array integrity checks. The
default sequence (AIS = 0) is meant to replicate sequences normal “user” code follows, and thoroughly checks
the read propagation paths. This sequence is proprietary. The alternative sequence (AIS = 1) is just logically
sequential.
It should be noted that the time to run a sequential sequence is significantly shorter than the time to run the
proprietary sequence. If MRE is set, AIS has no effect.
0 Array integrity sequence is proprietary sequence.
1 Array integrity sequence is sequential.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
12-25