PXR40RM Datasheet, PDF (1293/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
Burst Starting Address
D_ADD[27:28]
00
01
10
11
Table 30-13. Wrap Bursts Order
Burst Order
(Assuming 32-bit Port Size)
word0 -> word1 -> word2 -> word3 -> word4 -> word5 -> word6 -> word7
word2 -> word3 -> word4 -> word5 -> word6 -> word7 -> word0 -> word1
word4 -> word5 -> word6 -> word7 -> word0 -> word1 -> word2 -> word3
word6 -> word7 -> word0 -> word1 -> word2 -> word3 -> word4 -> word5
The general case of burst transfers assumes that the external memory has 32-bit port size and 8-word burst
length. The EBI can also burst from 16-bit port size memories, taking twice as many external beats to fetch
the data as compared to a 32-bit port with the same burst length. The EBI can also burst from 16-bit or
32-bit memories that have a 4-word burst length (BL=1 in the appropriate Base Register). In this case, two
external 4-word burst transfers (wrapping on 4-word boundary) are performed to fulfill the internal 8-word
request¹. This operation is considered atomic by the EBI, so the EBI does not allow other unrelated master
accesses or bus arbitration to intervene between the transfers. For more details and a timing diagram, see
Section 30.4.2.6.3, Small Access Example #3: 32-byte Read to 32-bit Port with BL=1.
During burst cycles, the D_BDIP (Burst Data In Progress) signal is used to indicate the duration of the
burst data. During the data phase of a burst read cycle, the EBI receives data from the addressed slave. If
the EBI needs more than one data, it asserts the D_BDIP signal. Upon receiving the data prior to the last
data, the EBI negates D_BDIP. Thus, the slave stops driving new data after it receives the negation of
D_BDIP on the rising edge of the clock. Some slave devices have their burst length and timing
configurable internally and thus may not support connecting to a D_BDIP pin. In this case, D_BDIP is
driven by the EBI normally, but the output is ignored by the memory and the burst data behavior is
determined by the internal configuration of the EBI and slave device. When the TBDIP bit is set in the
appropriate Base Register, the timing for D_BDIP is altered. See Section 30.4.2.5.1, TBDIP Effect on
Burst Transfer for this timing.
Since burst writes are not supported by the EBI², the EBI negates D_BDIP during write cycles.
1. This case (of 2 external burst transfers being required) applies only to AMBA data bus width of 64 bits.
2. Except for the special case of a 32-bit non-chip-select access in 16-bit data bus mode. See Section 30.4.2.9,
Non-Chip-Select Burst in 16-bit Data Bus Mode.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
30-31