PXR40RM Datasheet, PDF (199/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
Address: SIU_BASE + 0x0018
Access: R/W
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R _NMI 0
0
0
0
0
0
0 _NMI 0
0
0
0
0
0
0
W ^SEL8
SEL0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-6. DMA/Interrupt Request Enable Register (SIU_DIRER)
The following table describes the fields in the DMA interrupt request enable register:
Table 7-12. SIU_DIRER Bit Field Descriptions
Field
Description
0
NMISEL8
Non Maskable Interrupt / Critical Interrupt Selection (NMI comes from external pin). SIU generates two
specific sources of interrupt to the core, one of them is defined as critical interrupt and the other is defined as
non maskable interrupt (NMI). The NMISEL bit selects which signal receives the IRQ from the pin.
0 NMI is enabled (IVOR1 core exception)
1 Critical interrupt is enabled (IVOR0 core exception)
Note: NMISEL8 is a write once bit.
1–7 Reserved
8
NMISEL0
Non Maskable Interrupt / Critical Interrupt Selection (NMI comes from watchdog timer, SWT). SIU generates
two specific sources of interrupt to the core, one of them is defined as critical interrupt and the other is defined
as non maskable interrupt (NMI).
0 NMI is enabled (IVOR1 core exception)
1 Critical interrupt is enabled (IVOR0 core exception)
Note: NMISEL0 is a write once bit.
9–15 Reserved
16–31
EIREn
External interrupt request enable n. Enables the assertion of the interrupt request from the SIU to the interrupt
controller when an edge-triggered event occurs on the IRQ[n] pin.
0 External interrupt request is disabled.
1 External interrupt request is enabled.
Note: EIRE[0:3] can optionally enable DMA requests instead of IRQs.
7.3.1.6 DMA/Interrupt Request Select Register (SIU_DIRSR)
The SIU_DIRSR selects between a DMA or interrupt request for events on the IRQ[0]–IRQ[3] inputs. If
the IRQ flag bits are set in the external IRQ status register (SIU_EISR) and the DMA/interrupt request
enable register (SIU_DIRER), then the select bit in the DMA interrupt request select register
(SIU_DIRSR) determines whether a DMA or interrupt request is asserted.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-17