PXR40RM Datasheet, PDF (1010/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Table 27-12. EQADC_FISRx Field Description (continued)
Field
6
CFFFx
Description
CFIFO Fill Flag x. CFFFx is set when the CFIFOx is not full. When EQADC_IDCR[CFFEx] and CFFFx are both
asserted, an interrupt or a DMA request will be generated depending on the status of the CFFSx bit. When CFFSx
is negated (interrupt requests selected), software clears CFFFx by writing a “1” to it. Writing a “0” has no effect.
When CFFSx is asserted (DMA requests selected), CFFFx is automatically cleared by the EQADC when the
CFIFO becomes full.
0 CFIFOx is full.
1 CFIFOx is not full.
7–11
12
RFOFx
Note: Writing “1” to CFFFx when CFFSx is asserted (DMA requests selected) is not allowed.
Note: When generation of interrupt requests is selected (CFFSx=0), CFFFx must only be cleared in the ISR after
the CFIFOx push register is accessed.
Reserved
RFIFO Overflow Flag x. RFOFx indicates an overflow event on RFIFOx. RFOFx is set when RFIFOx is already full,
and a new data is received from the on-chip ADCs. The RFIFOx will not overwrite older data in the RFIFO, and
the new data will be ignored. When EQADC_IDCR[RFOIEx] and RFOFx are both asserted, the EQADC generates
an interrupt request.
Apart from generating an independent interrupt request for an RFIFOx overflow event, the EQADC also provides
a combined interrupt at which the Result FIFO Overflow Interrupt, the Command FIFO Underflow Interrupt, and
the Command FIFO Trigger Overrun Interrupt requests of ALL CFIFOs are ORed. When RFOIEx, CFUIEx, and
TORIEx are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags
becomes asserted: RFOFx, CFUFx, and TORFx (assuming that all interrupts are enabled). See Section 27.7.8,
EQADC DMA/Interrupt Request, for details.
Write “1” to clear RFOFx. Writing a “0” has no effect.
13
14
RFDFx
0 No RFIFO overflow event occurred.
1 An RFIFO overflow event occurred.
Reserved
RFIFO Drain Flag x. RFDFx indicates if RFIFOx has valid entries or not. RFDFx is set when the RFIFOx has at
least one valid entry in it. When EQADC_IDCR[RFDEx] and RFDFx are both asserted, an interrupt or a DMA
request will be generated depending on the status of the RFDSx bit. When RFDSx is negated (interrupt requests
selected), software clears RFDFx by writing a “1” to it. Writing a “0” has no effect. When RFDSx is asserted (DMA
requests selected), RFDFx is automatically cleared by the EQADC when the RFIFO becomes empty.
0 RFIFOx is empty.
1 RFIFOx has at least one valid entry.
Note: Writing “1” to RFDFx when RFDSx is asserted (DMA requests selected) is not allowed.
Note: When the generation of interrupt requests is selected (RFDSx=0), RFDFx must only be cleared in the ISR
after the RFIFOx pop register is accessed.
15
Reserved
16–19
CFCTRx
CFIFOx Entry Counter. CFCTRx indicates the number of commands stored in the CFIFOx. When the EQADC
completes transferring a piece of new data from the CFIFOx, it decrements CFCTRx by one. Writing a word or any
bytes to the corresponding EQADC_CFPR increments CFCTRx by one. Writing any value to CFCTRx has no
effect.
27-28
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor