PXR40RM Datasheet, PDF (1197/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
This field controls the TCRCLK digital filter (see Section 29.3.5.5, TCRCLK Digital Filter),
determining whether the TCRCLK signal input (after a synchronizer) is filtered with the same filter
clock as the channel input signals (see Section 29.3.4.4, Enhanced Digital Filter - EDF) or uses the
eTPU clock divided by 2, and also whether the TCRCLK digital filter works in integrator mode or two
sample mode (see Table 29-9).
Table 29-9. TCRCLK Filter Clock/Mode
TCRCF
00
01
10
11
Filter Clock
eTPU clock divided by 2
filter clock of the channels
eTPU clock divided by 2
filter clock of the channels
Filter Mode
two sample
two sample
integrator
integrator
AM — Angle Mode Selection
This field enables the Enhanced Angle Counter logic to generate angle information (see eTPU
Reference Manual for details), and also select the tooth signal input and the channel used to process it,
as shown in Table 29-10. When EAC is not disabled by AM and neither TCR1 nor TCR2 are STAC
Clients, the EAC (eTPU Angle Clock) hardware provides angle information to the channels using the
TCR2 bus. When AM is reset (non-angle mode), the EAC operation is disabled, and its internal
registers can be used as general purpose. For more information, see eTPU Reference Manual.
Table 29-10. AM - Angle Mode Selection
Valu
e
00
01
10
11
TCR2 Value
Timebase (EAC operation disabled)
Angle Ticks
Tooth signal
Tooth processing
channel
not applicable
TCRCLK input
0
channel 1 input
1
channel 2 input
2
If TCR1 or TCR2 is a STAC Bus Client (see Section 29.3.5.3, STAC Interface), the EAC operation is
not allowed, and if AM is set the Angle Logic does not work properly.
NOTE
Changing AM may cause spurious transition detections on the channel
selected by AM, depending on the channel mode and state (see eTPU
Reference Manual for details). If AM must be changed with GTBE=1, the
recommended procedure is described in the eTPU Reference Manual.
TCR2P[0:5] — Timer Count Register 2 Prescaler Control
These bits are part of the TCR2 clocking system (see Section 29.3.5, Time Bases). TCR2 is clocked
from the output of a prescaler. The prescaler divides its input by (TCR2P+1) allowing frequency
divisions from 1 to 64. The prescaler input is the eTPU clock divided by 8 (in gated or non-gated clock
mode), or Internal Timebase input, or TCRCLK filtered input. This field has no effect on TCR2 in
Angle Mode.
TCR1CTL[0:1] — TCR1 Clock/Gate Control
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-29