PXR40RM Datasheet, PDF (393/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

13.3.2 Cache Registers
Core (e200z7) Overview
13.3.2.1 L1 Cache Control and Status Register 0 (L1CSR0)
The L1 Cache Control and Status Register 0 (L1CSR0) is a 32-bit register used for general control of the
data cache as well as providing general control over disabling ways in both caches. The L1CSR0 register
is accessed using a mfspr or mtspr instruction. The SPR number for L1CSR0 is 1010 in decimal. The
L1CSR0 register is shown below.
0
0
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1010; Read/Write; Reset - 0x0
Figure 13-1. L1 Cache Control and Status Register 0 (L1CSR0)
The L1CSR0 bits are described below.
Table 13-1. L1CSR0 Field Descriptions
Field
0–3
WID
4–7
WDD
8–10
Description
Way Instruction Disable.
0 The corresponding way in the instruction cache is available for replacement by
instruction miss line fills.
1 The corresponding way instruction cache is not available for replacement by
instruction miss line fills.
Bit 0 corresponds to way 0.
Bit 1 corresponds to way 1.
Bit 2 corresponds to way 2.
Bit 3 corresponds to way 3.
The WID bits may be used for locking ways of the instruction cache, and also are used
in determining the replacement policy of the instruction cache.
Way Data Disable.
0 The corresponding way in the data cache is available for replacement by data miss
line fills.
1 The corresponding way in the data cache is not available for replacement by data
miss line fills.
Bit 4 corresponds to way 0.
Bit 5 corresponds to way 1.
Bit 6 corresponds to way 2.
Bit 7 corresponds to way 3.
The WDD bits may be used for locking ways of the data cache, and also are used in
determining the replacement policy of the data cache.
Reserved¹
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-5