PXR40RM Datasheet, PDF (1387/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
31.17.2.5 Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)
The data trace end address registers define the end addresses for each trace channel.
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DATA TRACE END ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-48. Data Trace Start Address Registers (DTEA1, DTEA2)
Table 31-41 illustrates the range that is selected for data trace for various cases of DTSA being less than,
greater than, or equal to DTEA.
Table 31-41. Data Trace Address Range Options
Programmed Values
DTSA < or = DTEA
DTSA < or = DTEA
DTSA > DTEA
Range Control Bit Value
0
1
—
Range Selected
DTSA DTEA
 DTSA DTEA 
Invalid range, no trace
NOTE
DTSA must be less than (or equal to) DTEA to guarantee correct data
write/read traces. When the range control bit is 0 (internal range), accesses
to DTSA and DTEA addresses are traced. When the range control bit is 1
(external range), accesses to DTSA and DTEA are not traced.
31.17.2.6 Breakpoint / Watchpoint Control Register 1 (BWC1)
Breakpoint/watchpoint control register 1 controls attributes for generation of NXDM and NXFR
watchpoint number 1.
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BWE1 BRW1
W
BWR1 BWT1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-49. Break / Watchpoint Control Register 1 (BWC1)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31-71