PXR40RM Datasheet, PDF (473/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Memory Protection Unit (MPU)
16.2.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn)
As noted in Section 16.2.2.4.3, MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2), it is expected
that because system software may adjust the access controls within a region descriptor
(MPU_RGDn.Word2) only as different tasks execute, an alternate programming view of this 32-bit entity
is desired. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAACn (alternate access control n) as stores to these locations do not affect the descriptor’s
valid bit.
The memory address therefore provides an alternate location for updating MPU_RGDn.Word2.
Address: MPU_BASE + 0x800 + (4*n) (MPU_RGDAACn)
0
R0
W
Reset
(n=0)
0
Reset
(n>0)
0
1
2
3
4
5
6
7
8
0
0
M6RE M6WE M5RE M5WE M4RE M4WE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
9
10
11
12
13
14
15
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
16
R0
W
Reset
(n=0)
1
Reset
(n>0)
0
17
18
19
20
21
22
23
24
25
26
27
28
0
0
0
0
0
0
0
0
0
M0PE M0SM
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-9. MPU RGD Alternate Access Control n (MPU_RGDAACn)
29
30
31
M0UM
r
w
x
0
0
0
0
0
0
Because the MPU_RGDAACn register is another memory mapping for MPU_RGDn.Word2, the field
definitions shown in Table 16-10 are identical to those presented in Table 16-8.
Table 16-10. MPU_RGDAAC Bit Field Descriptions
Field
Description
Note: For future code compatibility, do not change the value of reserved bits from their reset value
0–1 Reserved
2
4
6
MnRE
Bus Master ID n Read Enable. If set, this flag allows bus master ID n to perform read operations. If cleared, any
attempted read by bus master ID n terminates with an access error and the read is not performed.
Note: See Table 16-1 for the MPU Master ID list.
3
5
7
MnWE
Bus Master n Write Enable. If set, this flag allows bus master n to perform write operations. If cleared, any attempted
write by bus master n terminates with an access error and the write is not performed.
Note: See Table 16-1 for the MPU Master ID list.
8–25 Reserved
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
16-13