PXR40RM Datasheet, PDF (1123/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
Table 28-4. DECFILT_x_MCR Field Descriptions (continued)
Field
8
ODEN
9
ERREN
10
11–12
FTYPE
13
14–15
SCAL
16
IDIS
17
SAT
18–19
IO_SEL
Description
Output Data Interrupt Enable—Enables the Decimation Filter to generate interrupt requests on all new data
written to the filter Output buffer. This is independent of the IO_SEL field setting.
0 Output Data Interrupt Disabled
1 Output Data Interrupt Enabled
Error Interrupt Enable—Enables the Decimation Filter to generate interrupt requests based on the assertion of
the DECFILTER_MSR register error flags OVF, DIVR, SVR, OVR or IVR.
0 Error Interrupts Disabled
1 Error Interrupts Enabled
Reserved
Filter Type Selection bits—Selects the filter type.
00 Filter Bypass
01 IIR Filter - 1 x 4th order
10 FIR Filter - 1 x 8th order
11 Reserved
Reserved
Filter Scaling Factor—Selects the scaling factor used by the filter algorithm.
00 Scaling Factor = 1
01 Scaling Factor = 4
10 Scaling Factor = 8
11 Scaling Factor = 16
Input Disable—Disables the block input, so that writes to the input buffer have no effect and input DMA or
interrupt requests are not issued. Input disabling is needed to change the block configuration to or from cascade
mode.
0 Input enabled
1 Input disabled
Saturation Enable—Enables the saturation of the filter output. See Section 28.3.11, Saturation, for more details.
0 Disables Saturation
1 Enable Saturation
Input Data Source and Output Result Destination Selection—Selects the source of the input data to the
Decimation Filter, and the destination for the filter output result. The IO_SEL[1:0] encoding and associated
source and destination definitions is given below. Note that when Decimation Filters are cascaded to form larger
filters, the IO_SEL[1:0] field only is applicable to the input data source for the head filter in the cascade, and to
the output result destination for the tail filter in the cascade. Filters in the middle of the cascade receive input and
send output to their adjacent filters in the cascade. Regardless of the IO_SEL setting, the Decimation Filter input
and output buffer registers can be read by the CPU/DMA at any time, and the output buffer register is updated
in the case of the eQADC result destination. Note that the eQADC module has to be configured to send
conversion results to a decimation filter in addition to setting the IO_SEL field.
IO_SEL[1] IO_SEL[0]
Input Data Source
Output Result Destination
0
0
eQADC A/D conversion result
eQADC RFIFO
0
1
eQADC A/D conversion result Output Buffer Register (CPU/DMA)
1
0
Input Buffer Register (CPU/DMA) Output Buffer Register (CPU/DMA)
1
1
Input Buffer Register (CPU/DMA)
eQADC RFIFO
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-9