PXR40RM Datasheet, PDF (581/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
2. EDMA_x_TCD.START = 0, EDMA_x_TCD.ACTIVE = 1, EDMA_x_TCD.DONE = 0 (channel
is executing).
3. EDMA_x_TCD.START = 0, EDMA_x_TCD.ACTIVE = 0, EDMA_x_TCD.DONE = 0 (channel
has completed the minor loop and is idle), or
4. EDMA_x_TCD.START = 0, EDMA_x_TCD.ACTIVE = 0, EDMA_x_TCD.DONE = 1 (channel
has completed the major loop and is idle).
The best method to test for minor loop completion when using hardware initiated service requests is to
read the EDMA_x_TCD.CITER field and test for a change. The hardware request and acknowledge
handshakes signals are not visible in the programmer’s model.
The TCD status bits execute the following sequence for a hardware activated channel:
1. eDMA peripheral request asserts (channel service request via hardware).
2. EDMA_x_TCD.START = 0, EDMA_x_TCD.ACTIVE = 1, EDMA_x_TCD.DONE = 0 (channel
is executing).
3. EDMA_x_TCD.START = 0, EDMA_x_TCD.ACTIVE = 0, EDMA_x_TCD.DONE = 0 (channel
has completed the minor loop and is idle), or
4. EDMA_x_TCD.START = 0, EDMA_x_TCD.ACTIVE = 0, EDMA_x_TCD.DONE = 1 (channel
has completed the major loop and is idle).
For both activation types, the major loop complete status is explicitly indicated via the
EDMA_x_TCD.DONE bit.
The EDMA_x_TCD.START bit is cleared automatically when the channel begins execution, regardless of
how the channel was activated.
21.5.6.2 Active Channel TCD Reads
The eDMA will read back the true EDMA_x_TCD.SADDR, EDMA_x_TCD.DADDR, and
EDMA_x_TCD.NBYTES values if read while a channel is executing. The true values of the SADDR,
DADDR, and NBYTES are the values the eDMA engine is currently using in its internal register file and
not the values in the TCD local memory for that channel. The addresses (SADDR and DADDR) and
NBYTES (decrements to zero as the transfer progresses) can give an indication of the progress of the
transfer. All other values are read back from the TCD local memory.
21.5.6.3 Preemption Status
Preemption is available only when fixed arbitration is selected for both group- and channel-arbitration
modes. A preempt-able situation is one in which a preempt-enabled channel is running and a higher
priority request becomes active. When the eDMA engine is not operating in fixed group, fixed-channel
arbitration mode, the determination of the relative priority of the actively running and the outstanding
requests become undefined. Channel and group priorities are treated as equal (or more exactly, constantly
rotating) when round-robin arbitration mode is selected.
The EDMA_x_TCD.ACTIVE bit for the preempted channel remains asserted throughout the preemption.
The preempted channel is temporarily suspended while the preempting channel executes one iteration of
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-57