PXR40RM Datasheet, PDF (872/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Address: DSPI_BASE + 0x8
Access: R/W
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
SPI_TCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-4. DSPI Transfer Count Register (DSPI_TCR)
Table 25-6. DSPI_TCR Field Descriptions
Field
Description
0–15
SPI_TCNT
SPI Transfer Counter. SPI_TCNT is used to keep track of the number of SPI transfers made. The
SPI_TCNT field counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is
incremented every time the last bit of a SPI frame is transmitted. A value written to SPI_TCNT presets
the counter to that value. SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT
field is set in the executing SPI command. The Transfer Counter ‘wraps around’ i.e. incrementing the
counter past 65535 resets the counter to zero.
16–31 Reserved, should be cleared.
25.3.2.3 DSPI Clock and Transfer Attributes Registers 0–7
(DSPI_CTAR0–DSPI_CTAR7)
The DSPI_CTAR registers are used to define different transfer attribute configurations. SPI and DSI
transfers select which one of the DSPI_CTARs to get their transfer attributes from. The user must not write
to the DSPI_CTAR registers while the DSPI is in the Running state.
In Master Mode, the DSPI_CTAR0 - DSPI_CTAR7 registers define combinations of transfer attributes
such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. In Slave
Mode, a subset of the bitfields in the DSPI_CTAR0 and DSPI_CTAR1 registers are used to set the slave
transfer attributes. See the individual bit descriptions for details on which bits are used in Slave Modes.
When the DSPI is configured as a SPI Master, the CTAS field in the command portion of the TX FIFO
entry selects which of the DSPI_CTAR register is used. When the DSPI is configured as a SPI bus Slave,
the DSPI_CTAR0 register is used.
When the DSPI is configured as a DSI Master, the DSICTAS field in the DSPI DSI Configuration Register
(DSPI_DSICR), selects which of the DSPI_CTAR register is used. When the DSPI is configured as a DSI
bus Slave, the DSPI_CTAR1 register is used.
In CSI Configuration, the transfer attributes are selected based on whether the current frame is SPI data or
DSI data. SPI transfers in CSI Configuration follow the protocol described for SPI Configuration, and DSI
transfers in CSI Configuration follow the protocol described for DSI Configuration. CSI Configuration is
25-12
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor