PXR40RM Datasheet, PDF (195/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
The following table lists and describes the fields of the reset status register:
Table 7-8. SIU_RSR Bit Field Descriptions
Field
Description
0
PORS
Power-on reset status.
0 Another reset source was acknowledged by the reset controller since the last assertion of the power-on reset
input.
1 The power-on reset input to the reset controller was asserted and no other reset source was acknowledged
since the assertion of the power-on reset input except an external reset.
1
ERS
External reset status.
0 The last reset source acknowledged by the reset controller was not a valid assertion of the RESET pin.
1 The last reset source acknowledged by the reset controller was a valid assertion of the RESET pin.
2
LLRS
Loss-of-lock reset status.
0 The last reset source acknowledged by the reset controller was not a loss-of-PLL lock reset.
1 The last reset source acknowledged by the reset controller was a loss-of-PLL lock reset.
3
LCRS
Loss-of-clock reset status.
0 The last reset source acknowledged by the reset controller was not a loss-of-clock reset.
1 The last reset source acknowledged by the reset controller was a loss-of-clock reset.
4
WDRS
Core Watchdog timer/debug reset status.
0 The last reset source acknowledged by the reset controller was not a watchdog timer or debug reset.
1 The last reset source acknowledged by the reset controller was a watchdog timer or debug reset.
6
SWTRS
Platform software watch dog reset status.
0 The last reset source acknowledged by the reset controller was not a platform software watchdog timer or debug
reset.
1 The last reset source acknowledged by the reset controller was a platform software watchdog timer or debug
reset.
7–13 Reserved
14
SSRS
Software system reset status.
0 The last reset source acknowledged by the reset controller was not a software system reset.
1 The last reset source acknowledged by the reset controller was a software system reset.
15
SERF
Software external reset flag.
0 The software external reset input to the reset controller was not asserted, or this bit has been cleared by writing
a 1 to it.
1 The software external reset input to the reset controller was asserted while this bit was 0.
16
Weak pull configuration pin status
WKPCFG 0 The WKPCFG pin value latched during the last reset was a logical 0 and weak pulldown is the default setting.
1 The WKPCFG pin value latched during the last reset was a logical 1 and weak pullup is the default setting.
17–27 Reserved
28
ABR
Auto Baud Rate
0 Auto Baud Rate Disabled
1 Auto Baud Rate Enabled
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-13