PXR40RM Datasheet, PDF (175/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
caused by a reference clock failure or a PLL failure. If the reference fails, the PLL goes out of lock and
into self-clocked mode (SCM) (see Table 6-11). The PLL remains in SCM until the next reset. When the
PLL is operating in SCM, the PLL runs open loop at a default VCO frequency. The RFD will set to
divide-by-6 to ensure the clock presented to the system is well below the maximum allowable frequency
for the device. If the loss-of-clock condition is due to a PLL failure (i.e., loss of feedback clock), the PLL
reference becomes the system clock source until the next reset, even if the PLL regains itself and re-locks.
Table 6-11. Loss-of-Clock Summary
Clock Mode
System Clock
Source
before Failure
REFERENCE FAILURE
Alternate Clock Selected by
LOC Circuitry until Reset
PLL FAILURE
Alternate Clock Selected by
LOC Circuitry until Reset
PLL
PLL
PLL self-clocked mode
PLL reference
PLL Off
Ext. Clock(s)
None
NA
Note: The LOC circuit monitors the inputs to the PFD: reference and feedback clocks (see Figure 6-2).
A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures may be
simultaneous or the PLL may fail first. In either case, the reference clock failure takes priority and the PLL
attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. During SCM,
modulation is always disabled. If the PLL cannot operate in SCM, the system remains static until the next
reset. Both the reference and the PLL must be functioning properly to exit reset.
6.4.3.3 PLL Normal Mode Without FM
In PLL mode, the system clocks are synthesized by the FMPLL by multiplying up the reference clock
frequency. It is critical that the system clock frequency remain within the range for the device (see PXR40
Microcontroller Data Sheet). The output of the FMPLL can be divided down in powers of 2 up to 64 to
reduce the system frequency with the ERFD. The ERFD is not contained in the feedback loop of the PLL,
so changing the ERFD bits does not affect FMPLL operation. Finally, the PLL can be frequency modulated
to reduce electromagnetic interference often associated with clock circuitry. Figure 6-2 shows the overall
block diagram for the PLL. Each of the major blocks is discussed briefly in the following sections.
6.4.3.3.1 Phase/Frequency Detector
The phase/frequency detector (PFD) is a dual-latch phase-frequency detector. It compares both the phase
and frequency of the reference clock and the feedback clock. The reference clock comes from the crystal
oscillator or an external clock source. The feedback clock comes from the VCO output divided down by
the EMFD in normal PLL mode.
When the frequency of the feedback clock equals the frequency of the reference clock (i.e., the PLL is
frequency locked), the PFD pulses the UP or DOWN signals depending on the relative phase of the two
clocks. If the falling edge of the reference clock leads the falling edge of the feedback clock, then the UP
signal is pulsed. If the falling edge of the feedback clock leads the falling edge of the reference clock, then
the DOWN signal is pulsed. The width of these pulses relative to the reference clock is dependent on how
much the two clocks lead or lag each other. After phase lock is achieved, the PFD continues to pulse the
UP and DOWN signals for a very short duration during each reference clock cycle. These short pulses
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
6-17