PXR40RM Datasheet, PDF (1231/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
For parameters shared by both Engines, eTPU provides hardware semaphores. Coherency is assured
given the semaphores are used to prevent concurrent access to the changing parameters. Microengine can
request semaphores using specific microinstructions.
Neither Host nor CDC have access to the hardware semaphores, but they can be combined with microcode
transfer mechanisms if Host must coherently access parameters which are also shared by both Engines.
29.3.4.1 Host Side Atomic Access
Host side atomic accesses can be achieved by either of following ways:
• for one parameter, the SDM should be accessed by 32-bit-wide data transfers to ensure coherency
• for two parameters only, using the Coherent Dual Parameter Controller.
• indirectly, for any number of parameters, by requesting microcode to coherently access SDM in its
behalf. The host side atomicity problem becomes, then, a microengine side atomicity problem.
Some methods that use this approach to achieve coherency are described in Section 29.4.1,
Multiple Parameter Coherency Methods.
29.3.4.2 Coherent Dual-parameter Controller - CDC
Dual-parameter coherency is supported by a Coherent Dual-parameter Controller hardware - CDC, which
contends with microengine for SDM access. CDC atomically transfers, upon Host’s command, two
parameters from one area of the SDM to another. One area is a temporary (buffer) area, where the two
parameters are directly read or written by the Host. This temporary area has to begin in an SDM address
multiple of 2 words, and the two parameters must be sequential. The other area is the channel parameter
area where the microcode normally accesses the parameters, usually with the channel relative address
mode (see the eTPU Reference Manual for details). In this area, the parameters transferred by CDC don’t
have to be sequential. A transfer from the temporary area to the channel area, when the Host sends data to
the channel, is called a write transfer. Inversely, in a read transfer the parameters are copied from the
channel area to the temporary area (channel to Host).
Coherency is guaranteed by the SDM access contention rules implemented in the SDM arbiter. CDC
transfers are coherent in respect to the two Engines, so the target parameters in the channel area may be
shared by channels on them both. During CDC operation, the Host may suffer from 3 up to 11 eTPU clocks
wait states¹, and the Microengine(s) may suffer up to 2 microcycle wait-states². CDC accesses are atomic
with respect to Microengine(s) accesses to the SDM. Even when neither engine is in TST, CDC may suffer
up to 4 eTPU clock internal wait-states from SDM arbiter, meaning 9 slave wait-states to Host, so that it
does not break atomic back-to-back accesses from microengine(s). CDC also cannot break TST preload
accesses. Host can initiate CDC back-to-back transfers: there is no need of idle slave cycles between two
transfers.
1. A microengine access to the SDM in the moment CDC is performing the transfer may suffer a maximum of two wait-states.
1. The maximum number of Host wait states on CDC occurs when both microengines overlap their TSTs, delayed 3 eTPU
clocks from each other.
2. One microcycle takes two eTPU clocks. Microengines get wait-states in multiples of microcycles, while Host and CDC
wait-states are multiples of eTPU clocks.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-63