PXR40RM Datasheet, PDF (559/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
1,... channel 31 (63 for eDMA_A). The definitions of the TCD are presented as eight 32-bit values.
Table 21-20 is a field list of the basic TCD structure.
Table 21-20. TCDn 32-bit Memory Structure
eDMA Offset
0x1000+(32 x n)+0x0000
0x1000+(32 x n)+0x0004
0x1000+(32 x n)+0x0008
0x1000+(32 x n)+0x000C
0x1000+(32 x n)+0x0010
0x1000+(32 x n)+0x0014
0x1000 (32 x n) 0x0018
0x1000+(32 x n)+0x001c
TCDn Field
Source address (saddr)
Transfer attributes
Signed source address offset (soff)
Inner minor byte count (nbytes)
Last source address adjustment (slast)
Destination address (daddr)
Current major iteration count (citer)
Signed destination address offset (doff)
Last destination address adjustment / scatter-gather address (dlast_sga)
Beginning major iteration count (biter)
Channel control/status
Figure 21-24 and Table 21-21 define the fields of the TCDn structure.
Word
Offset _{0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31}
0x0000
SADDR
0x0004
0x0008
SMOD
SSIZE
DMOD
DSIZE
NBYTES¹
SOFF
0x0008
MLOFF or NBYTES ¹
NBYTES¹
0x000C
0x0010
SLAST
DADDR
0x0014
CITER or
CITER.LINKCH
CITER
DOFF
0x0018
DLAST_SGA
0x001C
BITER or
BITER.LINKCH
BITER
BWC MAJOR LINKCH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 21-24. TCD Structure
1 _{The fields implemented in Word 2 depend on whether EDMA_x_MCR(EMLM) is set to 0 or 1. Refer to Table 21-4.}
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-35