PXR40RM Datasheet, PDF (468/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Memory Protection Unit (MPU)
Offset: MPU_BASE + 0x00014 (MPU_EDR0)
MPU_BASE + 0x001C (MPU_EDR1)
MPU_BASE + 0x0024 (MPU_EDR2)
MPU_BASE + 0x002C (MPU_EDR3)
Access: User read only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
E
EACD
EPID
EMN
EATTR R
W
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 16-4. MPU Error Detail Register, MPU Port n (MPU_EDRn)
Table 16-5. MPU_EDR Bit Field Descriptions
Field
Description
0–15
EACD
Error Access Control Detail. This 16-bit read-only field implements one bit per region descriptor and is an indication
of the region descriptor hit logically-ANDed with the access error indication. The MPU performs a
reference-by-reference evaluation to determine the presence/absence of an access error. When an error is
detected, the hit-qualified access control vector is captured in this field.
If the MPU_EDRn register contains a captured error and the EACD field is all zeroes, this signals an access that did
not hit in any region descriptor. All non-zero EACD values signal references that hit in a region descriptor(s), but
failed due to a protection error as defined by the specific set bits.
16–23 Error Process Identification. This 8-bit read-only field records the process identifier of the faulting reference. The
EPID process identifier is typically driven by processor cores only; for other bus masters, this field is cleared.
24–27 Error Master Number. This 4-bit read-only field records the logical master number of the faulting reference. This field
EMN is used to determine the bus master that generated the access error.
28–30
EATTR
Error Attributes. This 3-bit read-only field records attribute information about the faulting reference. The supported
encodings are defined as:
000 User mode, instruction access
001 User mode, data access
010 Supervisor mode, instruction access
011 Supervisor mode, data access
All other encodings are reserved. For non-core bus masters, the access attribute information is typically wired to
supervisor, data (0b011).
31
ERW
Error Read/Write. This 1-bit read-only field signals the access type (read, write) of the faulting reference.
0 Read
1 Write
16.2.2.4 MPU Region Descriptor n (MPU_RGDn)
Each 128-bit (16 byte) region descriptor specifies a given memory space and the access attributes
associated with that space. The descriptor definition is fundamental to the operation of the MPU.
The region descriptors are organized sequentially in the MPU’s programming model and each of the four
32-bit words are detailed in the subsequent sections.
16-8
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor