PXR40RM Datasheet, PDF (667/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
• Receive FIFO Watermark and Selection Register (RFWMSR)
• Receive FIFO Start Index Register (RFSIR)
• Receive FIFO Depth and Size Register (RFDSR)
• Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
• Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
• Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
• Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
• Receive FIFO Range Filter Configuration Register (RFRFCFR)
22.6.3.7.2 Receive FIFO Control Data
The application can access the FIFOs at any time using the control bits in the following registers:
• Global Interrupt Flag and Enable Register (GIFER)
• Receive FIFO Fill Level and POP Count Register (RFFLPCR)
22.6.3.7.3 Receive FIFO Status Data
The current status of the receive fifo is provided in the following register:
• Global Interrupt Flag and Enable Register (GIFER)
• Receive FIFO A Read Index Register (RFARIR)
• Receive FIFO B Read Index Register (RFBRIR)
• Receive FIFO Fill Level and POP Count Register (RFFLPCR)
22.6.4 FlexRay Memory Layout
The controller supports a wide range of possible layouts for the flexray memory. Two basic layout modes
can be selected by the FIFO address mode bit MCR[FAM].
22.6.4.1 FlexRay Memory Layout (MCR[FAM] = 0)
Figure 22-107 shows an example layout for the FIFO address mode MCR[FAM]=0. In this mode, the
following set of rules applies to the layout of the flexray memory:
• The flexray memory is one contiguous region.
• The flexray memory size is maximum 64 Kbytes.
• The flexray memory starts at a 16 byte boundary
The flexray memory contains three areas: the message buffer header area, the message buffer data area,
and the sync frame table area.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-83