PXR40RM Datasheet, PDF (63/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Chapter 2
Memory Map
2.1 Introduction
All addresses in the device, including those that are reserved, are identified in the following tables. The
addresses represent the physical addresses assigned to each block. Logical addresses are translated by the
MMU into physical addresses.
Under software control of the Memory Management Unit (MMU), the logical addresses allocated to IP
blocks may be changed on a minimum of a 4 KB boundary. Table 2-1 shows this device’s memory map.
Table 2-1. PXR40 memory map
Block
Flash (4 MB)
Reserved
Flash B Shadow Block
Reserved
Flash A Shadow Block
Emulation re-mapping of flash
External Development Memory
Internal Standby SRAM (32 KB)
Internal SRAM (224 KB)
Reserved
Peripheral Bridge A Registers
Reserved
FMPLL
EBI Configuration
Flash A Configuration
Flash B Configuration
SIU
Reserved
eMIOS
Reserved
Address
0x0000_0000—0x003F_FFFF
0x0040_0000—0x00EF_BFFF
0x00EF_C000—0x00EF_FFFF
0x00F0_0000—0x00FF_BFFF
0x00FF_C000—0x00FF_FFFF
0x0100_0000—0x1FFF_FFFF
0x2000_0000—0x3FFF_FFFF
0x4000_0000—0x4000_7FFF
0x4000_8000—0x4003_FFFF
0x4004_0000—0xC3EF_FFFF
0xC3F0_0000—0xC3F0_3FFF
0xC3F0_4000—0xC3F7_FFFF
0xC3F8_0000—0xC3F8_3FFF
0xC3F8_4000—0xC3F8_7FFF
0xC3F8_8000—0xC3F8_BFFF
0xC3F8_C000—0xC3F8_FFFF
0xC3F9_0000—0xC3F9_3FFF
0xC3F9_4000—0xC3F9_FFFF
0xC3FA_0000—0xC3FA_3FFF
0xC3FA_4000—0xC3FB_BFFF
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
2-1