PXR40RM Datasheet, PDF (1221/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.3.2.5 Host Service Requests
Host CPU can request immediate service from a channel by writing a non-zero value to the Host Service
Request register field - HSR (see Section 29.2.10.3, ETPUCxHSRR - eTPU Channel x Host Service
Request Register). There is one HSR field for each channel, so that writing to it generates a Service
Request to the respective channel only. A zero value in HSR means no Host Service Request is pending
for the channel.
HSR value turns to 000 automatically at the end of microengine service for that channel, but only if the
thread started due to an HSR.
The meaning of a non-zero HSR value depends on the Function assigned for the channel. These bits are
part of the conditions which select the Function entry point, and cannot be tested by microcode. For more
details, refer to the eTPU Reference Manual.
If Host writes HSR=000 when a thread for the same channel is already running, the thread runs until the
end and is not aborted. If Host writes HSR>000 when an HSR thread for the same channel is already
running, HSR value resets at the end of the thread, and no new HSR will be pending. If HSR is written
before its value is resolved by the scheduler during TST, the entry point will obey the new HSR value, and
if this new value is 000, no service thread is executed for the HSR.
The scheduling of HSRs is completely asynchronous with Host accesses, and there is no race-free manner
to change an HSR value before service thread execution, so generally the safe way is: write HSR>0 only
when HSR=0. Error recovery or emergency host procedures may require one to the safely abort service
and reset channel state when an HSR is already pending or executing. In these cases, the procedure below
should be followed:
1. Disable the channel, writing CPR=00 in register ETPUCxCR. That will prevent any pending HSR
to be serviced.
2. Check if the channel is currently being serviced, reading its service status bit in register
ETPUCSSR. If it is, wait for the time necessary to finish the service pending, or check again until
HSR == 0, or channel service bit in ETPUCSSR is cleared.
3. Write HSR with the error recover value. This value should, possibly combined with other
host-defined flags in SDM or FM bits, initiate a channel reset or error recovery procedure.
4. Re-enable the channel, writing CPR value > 0 in register ETPUCxCR.
29.3.2.6 SCM access
Only Host can access SCM as data. Depending on the specific device, SCM may be implemented as a
RAM or ROM. This determines Host accesses to the SCM as shown below.
29.3.2.6.1 SCM RAM Implementations
When SCM is implemented as RAM, the Host may read or write to SCM by setting ETPUMCR bit VIS=1.
If VIS=0 and Host tries to access SCM space, a bus error is issued, writes are ineffective and read data is
meaningless. Both Engines must be stopped or halted to set VIS=1.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-53