PXR40RM Datasheet, PDF (254/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
Address: SIU_BASE + 0x9A8
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
HLTACK
W
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
HLTACK
W
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 7-27. Halt Acknowledge Register (SIU_HLTACK)
Table 7-47. HALT Acknowledge Register Field Descriptions
Field
Description
0-31
HLTACK
Halt Acknowledge
The HLTACK bits acknowledge halt for specific modules. Each bit corresponds to a
separate module as mapped below:
0 CPU and platform¹
1 rsvd
2 rsvd
3 rsvd
4 rsvd
5 eTPU_A, eTPU_B
6 NPC
7 EBI
8 eQADCs: eQADC_A and eQADC_B
9 rsvd
10 eMIOS_A
11 DECFILTs (decimation filters)
12 rsvd
13 PIT
14 rsvd
15 rsvd
16 FlexCAN_D
17 FlexCAN_C
18FlexCAN_B
19 FlexCAN_A
20 DSPI_D
21 DSPI_C
22 DSPI_B
23 DSPI_A
24 rsvd
25 rsvd
26 rsvd
27 rsvd
28 rsvd
29 eSCI_C
30 eSCI_B
31 eSCI_A
1 _{Stops all CPU clocks, stops the platform, excluding interrupt controller and watchdogs.}
7-72
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor