PXR40RM Datasheet, PDF (666/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
message buffers and the number of individual message buffers that are used. For more details, see
Section 22.6.3.1.1, Individual Message Buffer Segments.
Specific Configuration Data
The set of message buffer specific configuration data for individual message buffers is located in the
following registers.
• Message Buffer Configuration, Control, Status Registers (MBCCSRn)
The MCM, MBT, MTD bits configure the message buffer type.
• Message Buffer Cycle Counter Filter Registers (MBCCFRn)
The MTM, CHA, CHB bits configure the transmission mode and the channel assignment. The
CCFE, CCFMSK, and CCFVAL bits and fields configure the cycle counter filter.
• Message Buffer Frame ID Registers (MBFIDRn)
For a transmit message buffer, the FID field is used to determine the slot in which the message in
this message buffer will be transmitted.
• Message Buffer Index Registers (MBIDXRn)
This MBIDX field provides the index of the message buffer header field of the physical message
buffer that is currently associated with this message buffer.
22.6.3.5 Individual Message Buffer Control Data
During normal operation, each individual message buffer can be controlled by the control and trigger bits
CMT, LCKT, EDT, and MBIE in the Message Buffer Configuration, Control, Status Registers
(MBCCSRn).
22.6.3.6 Receive Shadow Buffer Configuration Data
Before frame reception into the individual message buffers can be performed, the receive shadow buffers
must be configured. The configuration data are provided by the Receive Shadow Buffer Index Register
(RSBIR). For each receive shadow buffer, the application provides the message buffer header index. When
the protocol is in the POC:normal active or POC:normal passive state, the receive shadow buffers are
under full controller control.
22.6.3.7 Receive FIFO Control and Configuration Data
This section describes the configuration and control data for the two receive FIFOs.
22.6.3.7.1 Receive FIFO Configuration Data
The controller provides two functional independent receive FIFOs, one per channel. The FIFOs have a
common subset of configuration data:
• Receive FIFO System Memory Base Address Register (RFSYMBADR)
• Receive FIFO Periodic Timer Register (RFPTR)
Each FIFO has its own set of configuration data. The configuration data are located in the following
registers:
22-82
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor